06 set - Italia
Luxoft
Project descriptionWorking for a global provider of network test, monitoring and assurance solutions for telecommunications, cloud, enterprises, first responders, military, aerospace, and railway. a leader in light management technologies for 3 D sensing, anti-counterfeiting, consumer electronics, industrial, automotive, government and aerospace applications. Employees working on this project are passionate about supporting customer success and we welcome people who bring their best every day to the company – to question, to collaborate and to push for solutions that will delight our customers.
Responsibilities
We are seeking a Principal/Staff-level FPGA Engineer — a recognized technical authority — to own FPGA architecture for our state-of-the-art Communications Test & Measurement products.The successful candidate will define and drive end-to-end FPGA architecture, including make/buy tradeoffs on IP, floorplanning and timing closure strategy for multi-gigabit designs, and DFX approach, using Verilog/System Verilog/VHDL and industry-leading simulation, synthesis, place-and-route,
and formal/UVM verification tools. This person will serve as the final technical escalation point for FPGA design and debug issues across the team, mentor other FPGA engineers, and lead root-cause debug of silicon and board bring-up issues that could not be resolved elsewhere.
Skills
Must haveBS or MS degree in Electrical and/or Computer Engineering with a minimum of 12-15 years of relevant experience, including at least 5+ years specifically architecting and closing timing on multi-Gbps Ser Des/transceiver-based FPGA designs.Demonstrated expertise architecting and implementing high-speed FPGA designs using Verilog/System Verilog and/or VHDL required.Deep, hands-on expertise with FPGA transceivers, hard IP, and PLLs — including timing closure, equalization, and link debug at multi-Gbps rates — required (not incidental exposure).Demonstrated experience closing timing and debugging link-layer
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