07 set - Pavia
Marvell Technology
About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Storage, Security, and Networking. You’ll be part of a small analog team making a big impact on this organization. Additionally, Marvell has the perfect size and scale for you to learn several aspects of engineering that will be new to you, but also have the time and freedom to dive deep into the details of your specialization on most projects.
The successful candidate will be self-motivated, willing to learn exciting new technologies, and be able to work effectively within a talented group of individuals. You will gain exposure to a variety of IC design engineering skills and tools during your internship.
The Internship would be for a duration of up to 6 months and will take place in our Pavia office.
What You Can Expect
Learn the use of all the different IC layout development CAD and physical verification tools.
Train on Mask/layout design using Cadence Virtuoso EXL/Custom Compiler Synopsys using circuit design as input.
Learn design rules of advanced CMOS technology nodes (16nm to 3nm).
Run DRC/LVS checks.
Learn Electromigration/IR drop (EMIR) concepts for analog IC layout.
Optimize layout designs in terms of area and parasitic R,C.
Work with team and collaborate effectively with people for effective outcomes.
Have routine meetings with your technica
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