Ams Verification Engineer
Pubblicato il 06-09-2026 - STMicro in Catania
ph3LA NOSTRA STORIA /h3pNoi di ST crediamo nel potere della tecnologia di guidare l'innovazione e avere un impatto positivo sulle persone, sulle imprese e sulla società.
Siamo un'azienda globale di semiconduttori e la nostra tecnologia avanzata e i nostri chip costituiscono la parte nascosta del mondo in cui viviamo oggi.
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Persone con passione e desiderio di andare oltre i confini e guidare l'innovazione, sbloccando al tempo stesso il proprio potenziale.
/ph3AMS Verification Engineer /h3pWe are looking for a talented engineer to join our AMS Verification team and contribute to the functional verification of advanced mixed-signal ASICs for applications including PMICs, wireless charging, battery charging, display drivers, and other complex integrated solutions.
/ppIn this role, you will collaborate closely with analog, digital, and system-level designers to develop and validate high-quality behavioral models and System Verilog real-number models used in AMS and DMS verification flows.
You will work on models that may be hierarchical or flat, as well as black-box or white-box, depending on the verification needs and project phase.
/pulliPreparing and configuring mixed-signal simulation environments based on technical documentation /liliExecuting simulations and analyzing results with rigor and attention to detail /liliValidating outcomes in close cooperation with analog and digital design teams /liliProducing clear, structured technical documentation to present results, assumptions,
and conclusions /liliContributing to the continuous evolution of verification methodologies and simulation flows in an RD environment /li /ulh3Desired profiles /h3ulliMaster's degree in Electrical, Electronic, or Computer Engineering /liliStrong ability to understand the architecture and behavior of complex electronic systems /liliSolid programming skills and an analytical mindset /liliStrong collaboration skills and a proactive attitude /liliExperience with System Verilog real-number modeling is highly valued /liliFamiliarity with mixed-signal simulation platforms such as:ulliMentor Questa/ADMS /liliCadence Xcelium/AMS /liliSynopsys VCS/AMS /li /ul /liliKnowledge of VHDL, Verilog, Verilog-AMS, or System Verilog is a plus /li /ulpThis role is ideal for someone who thrives in a technical, high-impact environment and is motivated by the opportunity to shape the verification of next-generation mixed-signal products.
/ppThe expected salary range for this position is €****** - €****** gross annual salary (RAL), plus variable pay relevant for the role.
/ppIn accordance with the EU Pay Transparency Directive and applicable Italian legislation, this compensation range has been determined based on objective, gender-neutral criteria, including job responsibilities, required skills, relevant experience, qualifications, and market benchmarks.
Placement within the range will depend on the candidate's profile and demonstrated competencies.
The final offer will be made in compliance with the applicable National Collective Bargaining Agreement (CCNL), where relevant, and our internal compensation policies.
We are committed to equal pay for equal work and equal opportunities for all candidates.
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Unisciti a noi e inizia il futuro!
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