Junior Electronics Design Engineer
Pubblicato il 09-09-2026 - Nxp Semiconductors in Italia
NXP’s Industrial & IoT Edge solutions range from the smallest MCUs to very high-performance processors to provide real-time insights and efficient automation when performance matters most. NXP’s advanced portfolio of edge processing solutions lets developers explore their most innovative ideas with confidence, enabling applications across the autonomous home, industrial automation, and personal electronics. NXP is building new teams in Catania to create high impact micro-controllers (MCU) as part of NXP’s intelligent AI at the Edge. This team will include a wide range of engineering talent from analog to SOC digital design. Full product development local will product world class products at a world class pace. As a Junior Physical Design Engineer, you will learn, execute and support the RTL-to-GDSII physical implementation flow for complex SoC/MCU designs on advanced nodes. Working closely with experienced engineers, you will play an active role in meeting performance, power, and area targets.
Support SOC-level floorplanning, power grid design, IO placement, Place & Route (P&R;),
Clock-Tree Synthesis (CTS) and physical verification (DRC, LVS, ERC, Antenna).
Assist with tool setup, static timing analysis (STA), basic timing constraints management, IR-drop, and Electromigration (EM) analysis.
Collaborate with RTL, DFT, and Analog design teams to facilitate smooth design hand-offs and integration.
Maintain and extend automation scripts (TCL, Python, Perl) to improve flow efficiency and design analysis.
Learn and apply state-of-the-art EDA tools and work with vendors to troubleshoot issues.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or related field. Solid understanding of digital design principles, semiconductor physics, and integrated circuit fundamentals. Familiarity with the basic IC design flow (from RTL concepts to GDSII layout). Understanding of basic timing analysis (setup/hold time), clock distribution, and low-power fundam