Engineering internship
Pubblicato il 10-09-2026 - STMicroelectronics Italia in Milano
At STMicroelectronics, we believe in the power of technology to drive innovation and make a positive impact on people, businesses, and society. As a global semiconductor company, our advanced technologies and chips form the hidden foundation of the world we live in today.
When you join ST, you will be part of a global business with more than 115 nationalities, present in 40 countries, and comprising over 50,000 diverse and dedicated creators and makers of technology around the world.
Developing technologies takes more than talent: it takes amazing people who understand collaboration and respect. People with passion and the desire to disrupt the status quo, drive innovation, and unlock their own potential.
Embark on a journey with us, where you can innovate for a future that we want to make smarter and greener, in a responsible and sustainable way. Our technology starts with you.
We are looking for a talented engineer to join our AMS Verification team and contribute to the functional verification of advanced mixed-signal ASICs for applications including PMICs,
In this role,
you will collaborate closely with analog, digital, and system-level designers to develop and validate high-quality behavioral models and System Verilog real-number models
used in AMS and DMS verification flows . You will work on models that may be hierarchical or flat , as well as black-box or white-box , depending on the verification needs and project phase.
Preparing and configuring mixed-signal simulation environments based on technical documentation
Validating outcomes in close cooperation with analog and digital design teams
Producing clear, structured technical documentation to present results, assumptions, and conclusions
Master’s degree in Electrical, Electronic, or Computer Engineering
Strong ability to understand the architecture and behavior of complex electronic systems
Strong collaboration skills and a proactive attitude
Experience with System Verilog real-number modeling is highly va