Analog IC Layout Engineer
Pubblicato il 10-09-2026 - HUAWEI TECHNOLOGIES ITALIA in San Giuseppe
About Huawei
Huawei is a leading global provider of information and communications technology (ICT) infrastructure and smart devices. With integrated solutions across four key domains – telecom networks, IT, smart devices, and cloud services – we are committed to bringing digital to every person, home and organization for a fully connected, intelligent world.
At Huawei, innovation focuses on customer needs. We invest heavily in basic research, concentrating on technological breakthroughs that drive the world forward. We have more than 200,000 employees , of which 55% are employed in R&D; , and we operate in more than 170 countries and regions.
Huawei invests more than 20% of revenues in R&D; every year: in the past 10 years our total R&D; investments exceed 150B USD .
By the end of 2025, Huawei held +150.000 active patents.
Who we are
- Our motto is "make it possible", we use our customer-centric obsession, our perseverance, our dedication and a continuous self-challenge to accomplish the most challenging goals and always raise the bar
- We think and execute very fast,
but we are never superficial and always guarantee the highest standards.
- We are obsessed about continuous improvement and about creating value for the company, for the employees and for society.
- We are a multicultural team where relationships are informal and direct and where cooperation and support are our daily keywords.
- We are a place where "results talk and ideas walk", good ideas are always welcome, but you have to take ownership and make them happen too.
- Openness and flexibility are our mantra.
The Opportunity
We are looking for analog IC layout engineers to expand our RFIC Design Team, to support our R&D; projects in the field of optical transceivers.
Key Responsibilities
- Physical layout and verification of high-performance Analog/RF ICs for mass-production integrated optical transceiver modules.
- Block-level to top-level layout, routing, layout verification, ERC verification, chip fini