[Permanent position] Senior IP subsystem SoC architect

11 set - Bologna
SiPearl

❓ About SiPearl…
SiPearl is the European fabless designer of sovereign secure high-performance energy-efficient CPUs for HPC, AI and data centres. These CPUs will help address strategic challenges in the fields of security, defence, medical research, energy, climate and engineering with a reduced environmental footprint.
In June 25, SiPearl completed the design of the most complex CPU ever designed in Europe, Rhea1. Featuring 80 Arm Neoverse V1 cores, with 61 billion transistors, it is currently in production at TSMC. Sipearl CPUs will equip the two first European exascale supercomputers belonging to EuroHPC JU: Rhea1 will be integrated into the JUPITER machine based in Germany and Rhea2 will be part of Alice Recoque in France.
Incubated within the European Processor Initiative (EPI) consortium and seed-funded by the European Union, SiPearl employs almost 200 people in :
- France (Maisons-Laffitte, Grenoble, Massy, Sophia Antipolis),
- Spain (Barcelona)
- and Italy (Bologna)

Following a €130 million Series A, the company has launched its Series B round.
About the role




In this role, you will work closely with the Design, Verification, Physical Implementation and Software teams to define, drive and evolve IP, subsystem and SoC architectures aligned with performance, cost, manufacturability and market requirements.
You will act as a technical authority and architectural reference, contributing to strategic decisions, cross-team alignment, external partnerships and team development.
About the missions
- Define IP, subsystem and SoC architectures to meet performance, silicon area, cost and manufacturing constraints
- Break down architectures into functional sub-blocks and write high-level architecture specifications, including interfaces and configuration mechanisms
- Participate in commercial IP selection and process technology choices
- Provide detailed definitions of software programming and configuration interfaces
- Support RTL, physical design, verification, virtu

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