Principal Verification Engineer
Pubblicato il 14-09-2026 - Onsemi in Turbigo
Principal Verification Engineer
Le seguenti informazioni hanno lo scopo di fornire ai potenziali candidati una migliore comprensione dei requisiti per questo ruolo.
Job Description
Principal Verification Engineer
Salary: Annual salary starting from €66,000, with the final offer depending on the candidate’s experience and qualifications.
Description
onsemi’s Power Management Division is seeking a Principal Verification Engineer with strong expertise in both block-level and SoC-level verification of integrated circuits. The ideal candidate has hands‑on experience with SystemVerilog, UVM and formal verification, and demonstrates a solid understanding of verification methodologies and coverage‑driven approaches.
You will work in a globally distributed team environment, extracting design intent from specifications and translating it into comprehensive verification strategies and plans to ensure maximum functional and code coverage.
Responsibilities
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- Develop SoC, subsystem, and block‑level verification plans based on power management IC specifications.
- Build, maintain, and enhance scalable and reusable verification environments.
- Drive verification quality to achieve target functional and code coverage metrics.
- Promote and implement innovative verification methodologies and technologies.
- Ensure comprehensive verification of both hardware and firmware components.
- Analyze, debug, and root‑cause verification failures efficiently.
- Lead verification activities across the full lifecycle, from planning to silicon validation readiness, with focus on pre‑silicon quality.
- Collaborate closely with cross‑functional teams and communicate effectively through coverage reviews, design/code reviews, and project updates.
Qualifications
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- BSEE/MSEE (or equivalent) with 7–10+ years of relevant experience.
- Strong expertise in SystemVerilog and UVM, including vertical reuse methodologies.
- Solid knowledge of industry‑standard EDA tools and verification flows.
- Proven experience in debugging complex verification issues.
- Hands‑on experience with Assertion‑Based Verification (SVA/PSL).
- Understanding of formal verification methodologies and their application to coverage closure.
- Proficiency in scripting languages such as Python, Tcl, or C‑shell.
- Experience in technical leadership and mentoring.
- Good understanding of analog and mixed‑signal IC architectures and integration challenges.
Nice to Have
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- Experience with power‑aware verification (UPF/UCF).
- Exposure to AI/ML techniques applied to verification.
- Experience in HW/SW co‑verification environments.
- Familiarity with requirements and project management tools (e.g., JAMA, JIRA). xysqume
- Experience with multi‑phase switching regulators or power management systems.
Benefits
More details about our company benefits can be found here: J-18808-Ljbffr