14 set - Bardi
Infineon Technologies
OverviewIn this role you will shape digital verification for mixed-signal designs, lead verification efforts, and collaborate across analog and digital teams to ensure robust RTL and gate-level validation.
You'll define verification plans, build advanced verification environments with SystemVerilog, UVM, and constrained random methods, and mentor junior engineers.
The position emphasizes driving methodological innovations and cross-functional impact within Infineon's R&D; for greener, smarter technology.
Retribuzione / Benefitscompetitive salaries
additional benefits based on performance
salary paid 14 times per year
higher compensation based on expertise
Hire4IFX eligible
ResponsabilitàDefine verification plans for digital verification of mixed-signal designs
Develop and improve verification environments using SystemVerilog, UVM, and constrained-random techniques
Execute RTL and gate-level tests and debug design/verification issues
Lead and coordinate other verification engineers on projects
Collaborate closely with analog and digital designers and other verification engineers
Mentor junior colleagues, consultants, and students
Drive improvements in methodologies and flows through innovation projects
Requisiti fondamentaliA university degree in Electrical Engineering, Computer Science, Information Technology or a similar discipline
6+ years of experience in Digital Verification
Leadership experience is a plus
Strong knowledge of SystemVerilog, UVM, and verification tools (Xcelium, Verdi, vManager or equivalents)
Good knowledge of RTL design (HDL) and digital or mixed-signal circuits
Knowledge of GIT, Python, and other programming languages as a plus
leadership and mentoring
cross-functional collaboration
problem-solving
SystemVerilog
UVM
Xcelium
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