Analog Mixed-Signal Verification Engineer
Pubblicato il 16-09-2026 - Altro in Viu'
Descrizione dell'offerta di lavoro INVENTVM is actively looking for a talented AMS Verification Engineer to join the design team.
Pronto/a a candidarsi? La preghiamo di leggere la descrizione almeno una volta prima di fare clic su "Candidati".In this role, you will be responsible for verifying mixed-signal and analog/mixed-signal (AMS) integrated circuits by developing robust verification environments, creating testbenches, and ensuring first-pass silicon success. You will work closely with analog and digital designers throughout the product development cycle.
Key Responsibilities Develop and execute verification plans for analog and mixed-signal IPs and SoCs
Create, maintain, and enhance AMS verification environments using industry-standard methodologies
Develop behavioral models of analog blocks using Verilog-A, Verilog-AMS, SystemVerilog RNM, or equivalent modeling languages
Design testbenches, stimuli, checkers, assertions, and coverage metrics to validate mixed-signal functionality
Perform functional, corner, Monte Carlo, and regression simulations
Collaborate with analog and digital design teams to identify, debug, and resolve functional issues
Support integration and verification of analog IPs within larger digital or mixed-signal SoCs
Analyze simulation results and communicate findings through clear technical reports
Contribute to verification methodology improvements, automation, and scripting
Support silicon bring-up and correlation between simulation and laboratory measurements when required
Required Qualifications Master's degree in Electrical Engineering, Electronics Engineering, or a related field
Solid understanding of analog and mixed-signal circuit fundamentals, including:> Operational amplifiers> Comparators> ADCs and DACs> PLLs (preferred)> Voltage regulatorsand references> Switched-capacitorcircuits
Experience with AMS simulation and verification tools (e.G., Cadence Virtuoso, Spectre, Xcelium)
Knowledge of Verilog-AMS, Verilog-A, SystemVerilog