R&D Senior System Engineer
Pubblicato il 17-09-2026 - Quintall in Quartino
Bij
Pronto/a a candidarsi? La preghiamo di leggere la descrizione almeno una volta prima di fare clic su "Candidati".
ABB helpen we industrieën efficiënter en schoner te werken en iedere medewerker draagt daaraan bij. U krijgt de ruimte om leiding te nemen, wordt ondersteund in uw ontwikkeling en zult trots zijn op de impact die we samen realiseren. Sluit u bij ons aan en help de wereld draaiende te houden.
Deze functie rapporteert aan:
Chapter Lead
In this role, you’ll help run what runs the world, by taking on meaningful work that drives real impact. We are looking for an R&D; Senior Hardware Engineer to join our Electrification business. The selected candidate will join a team working on UPS product lines.
Work model:
hybrid
Locations:
Quartino, Ticino, Switzerland
Your responsibilities:
Execute a variety of complex technology and engineering assignments. Understanding and applying applicable processes, standards, guidelines, and requirements, including architectural and design constraints.
Define technical specifications, perform circuit simulations,
and develop projects requiring expertise in analog, digital, and power systems.
Lead design optimization, identifying advanced technical, architectural, and circuitry solutions to maximize mechanical, electrical, and PCBA integration in collaboration with cross-functional product development teams
Develop and maintain comprehensive technical documentation for systems, components, and interfaces.
Qualifications for the Role
Master’s degree in Electrical or Electronics Engineering.
5+ years of experience with electrical systems and complex power electronic systems.
Proven experience in digital and analog circuit design and simulation and proven experience with EMI design, mitigation, and troubleshooting.
Strong knowledge of environmental, reliability, and safety requirements for industrial products.
Familiarity with product regulations and industry standards (including IEC and UL).
Proficiency in documentation s
