17 set - Pavia
Ams Italy
Your tasks
- Technical leader responsible for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC products
- Define digital subsystem architectures
- Lead RTL development and integration
- Drive design reviews and quality standards
- Support verification and implementation teams
- Mentor design engineers
Who we are looking for
- MSc or PhD in Electrical Engineering
18 set - Chiavari
Acrobatica
18 set - Fonzaso
Greta
18 set - Trento
Car Clinic
18 set - Nola
Demetra Formazione