17 set - Lodi
Infineon Technologies
Overview
In this role you lead the Digital Design team to deliver robust digital IPs and silicon bring-up for high-performance Analog/Mixed-Signal blocks. You collaborate with System Architecture, Analog, and Digital Physical Design teams to ensure cohesive, high-quality IP definition and integration. You'll own digital signoff across the RTL-to-GDS flow and tackle challenging digital functions like adaptive channel equalization at scale. This position blends leadership with hands-on design in a global, mission-driven company.
Retribuzione / Benefits
comprehensive total rewards package
hybrid workplace
competitive base salary with variable compensation
career development opportunities
inclusive and respectful work environment
global collaboration
Responsabilità
Lead the Digital Design team from specification to silicon bring-up
Design digital components for advanced Analog/Mixed-Signal IPs (high-speed SerDes, PHYs, PLLs)
Own digital signoff across RTL-to-GDS, LEC, linting, CDC/RDC, ATPG
Collaborate with System Architecture to implement complex digital functions (e.g., adaptive channel equalization)
Coordinate with Analog Design to ensure digital control and integration of analog blocks
Work with Digital Physical Design teams to achieve timing closure and signoff
Engage with internal customers and Verification teams to ensure IP quality and integration excellence
Requisiti fondamentali
10+ years of RTL design experience for Analog/Mixed-Signal IPs
Strong leadership mindset to guide engineering teams
Expert-level Verilog/SystemVerilog proficiency
Solid understanding of full digital design flow (RTL-to-GDS, LEC, linting, CDC/RDC, ATPG)
Good knowledge of Digital Test Methodologies
Experience in high-speed SerDes is highly valued
Fluency in English (mandatory)
leadership mindset
collaboration across cross-functional teams
clear communication in English
Verilog/SystemVerilog
RTL-to-GDS flow
LEC, CDC/RDC, ATPG
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