20 set - Godiasco Salice Terme
Ams Italy
Your tasks
- Technical leader responsible for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC products
- Define digital subsystem architectures
- Lead RTL development and integration
- Drive design reviews and quality standards
- Support verification and implementation teams
- Mentor design engineers
Who we are looking for
- MSc or PhD in Electrical Engineering
24 set - Milano
3240 Kyndryl Italia
24 set - Gaggiano
Ams Italy
24 set - Orta San Giulio
Cannavacciuologroup
24 set - Sommariva del Bosco
Bachecalavoro