22 set - Montebello della Battaglia
Ams Italy
ams Italy S.r.l. seeks a Technical Leader for architecture and RTL development of high-speed digital subsystems in communication ICs and mixed-signal SoCs. You will define architectures, lead RTL development, and drive design reviews while mentoring engineers.
Requirements include MSc/PhD in Electrical Engineering and 10+ years in digital IC design with RTL (Verilog/SystemVerilog). Knowledge of high-speed interfaces like UCIe/PCIe is a plus.
23 set - Roma
Meet and Greet Italy
23 set - Montone
Openjobmetis
23 set - Milano
MindMatch
23 set - Vigevano
Adecco Italia