22 set - Carezzano
Ams Italy
ams Italy S.r.l. is seeking a Technical Leader to own architecture and RTL development for high-speed digital subsystems in communication ICs and mixed-signal SoCs. You will define architectures, lead RTL efforts, and mentor engineers, ensuring design quality and timely delivery.
The role requires a PhD or MSc in Electrical Engineering with 10+ years in digital IC design, hands-on RTL in Verilog/SystemVerilog, and experience with high-speed interfaces and timing closure at advanced CMOS nodes.
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