22 set - Castellar Guidobono
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ams OSRAM is seeking a technical leader for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoCs. You will define digital architectures and lead RTL design using Verilog/SystemVerilog, guiding integration and design reviews at our Castellar site in Piemonte.
The role requires 10+ years of digital IC design, expertise in synthesis and timing analysis, and experience with high-speed interfaces; FinFET/FD-SOI know-how is a plus.
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