22 set - Roggione
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ams Italy S.r.l. seeks a Technical Leader for architecture and RTL development of high-speed digital subsystems in communication ICs and mixed-signal SoCs. You will define architectures and guide RTL design and integration.
Requirements include a MSc/PhD in Electrical Engineering with 10+ years in digital IC design and RTL expertise in Verilog/SystemVerilog; experience with PCIe/UCIe is a plus. You will drive design reviews, support verification and implementation teams, and mentor engineers in
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30 set - Torino
Mc Engineering
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