20 set - Bardi
Ams Italy
ams OSRAM is seeking an experienced engineering leader to architect and drive RTL development for high-speed digital subsystems in communication ICs and mixed-signal SoCs.
The role requires a strong background in RTL design (Verilog/SystemVerilog), CMOS process nodes, and timing analysis across fast interfaces.
You will mentor engineers and coordinate architecture reviews in a global R&D; environment.
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23 set - Roma
Meet and Greet Italy
23 set - Montone
Openjobmetis
23 set - Milano
MindMatch
23 set - Vigevano
Adecco Italia