VHDL Designer Engineer
Pubblicato il 22-09-2026 - Qascom in Veneto
Qascom is looking for a highly skilled VHDL Design Engineer to join our engineering team and contribute to the development of advanced digital systems for space and defence applications.
You will be involved in the design, implementation, verification, and validation of FPGA-based solutions for different applications, including mission-critical systems, ensuring compliance with stringent aerospace and defence standards.
This is an unique chance to contribute to the future of secure global navigation systems, working in a dynamic, international and innovative environment.
Key Responsibilities:
The VHDL Designer Engineer will:
- Design, develop, and optimize digital architecture using VHDL for FPGA platforms (e.g., Xilinx, Intel, Microchip);
- Perform simulation, debugging, and verification of digital designs using industry-standard tools;
- Collaborate with system, hardware, and software engineering teams to define requirements and ensure seamless integration;
- Prepare technical documentation, including design specifications, test procedures, and reports;
- Support reviews, audits, and qualification activities according to ECSS, DO-254, or equivalent standards;
- Contribute to continuous improvement of design processes, methodologies, and best practices.
What do you need:
- Master’s degree in Electronic Engineering;
- At least 2 years (out of 4) of professional experience gained in the design, simulation,
implementation, verification and validation of FPGA devices;
- Proven experience in programming in VHDL language and in the use of Xilinx Vivado tools, scripting in TCL language;
- Good knowledge of theory and design of digital electronic circuits and Digital Signal
Processing;
- Good knowledge of Matlab and/or Octave for co-simulation of algorithms implemented in FPGA knowledge;
- Eligibility for National Security Clearance;
- Advanced knowledge of written and spoken English.
Desired knowledge and skills:
- Experience in Cores development for Software Defined Radio applications;
- Memory-mapped / DMA core development experience for Xilinx Zynq;
- Experience in developing and debugging high-speed interfaces, for example JESD204,
PCIe, LVDS;
- Experience in developing low-level optimized cores, based on specific components of Xilinx FPGAs (DSP48E, I / O SerDes, Transceivers);
- Experience in in C ++ low-level programming of drivers and test applications of FPGA cores on Linux and bare-metal;
- Experience in defining pinout and PCB layout requirements of FPGA and SoC based circuits;
- Competence (even minimal) in the use of laboratory equipment (oscilloscope, logic analyzer) in troubleshooting activities;
- Desired knowledge of C and/or Python.
Job Information
Location: Bassano del Grappa (VI) | Hybrid Working
Contract Type: Full-time, Permanent Employment
Collective Labour Agreement: CCNL Metalmeccanico
Experience Level: Middle to Senior/Expert
Salary Range: €40,000 - €75,000 gross annual salary, depending on experience and qualifications.
Do you feel you don't match 100% of the requirements? Don't hesitate to apply anyway! Qascom is committed to supporting your career development.