22 set - Seggiano
Altro
ams OSRAM is seeking a technical leader responsible for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC products in Seggiano, Italy.
The ideal candidate holds an MSc or PhD in Electrical Engineering with 10+ years in digital IC design, RTL (Verilog/SystemVerilog), and experience with high-speed interfaces and clock-domain crossing. Strong leadership, design-review discipline, and mentoring are essential.
26 set - Lasa
Mpreis
26 set - Milano
Pirate Rocket
26 set - Martellago
R8srl
26 set - Roma
Pizzeria MAMI