Analog Mixed-Signal Verification Engineer

Vedi l’offerta su Go Lavoro: golavoro.it/annuncio-lavoro/80gs8r

Descrizione dell’offerta di lavoroDato l'elevato interesse per questa posizione, la preghiamo di candidarsi tempestivamente se il suo profilo è in linea con il ruolo.INVENTVM is actively looking for a talented AMS Verification Engineer to join the design team.In this role, you will be responsible for verifying mixed-signal and analog/mixed-signal (AMS) integrated circuits by developing robust verification environments, creating testbenches, and ensuring first-pass silicon success. You will work closely with analog and digital designers throughout the product development cycle.Key ResponsibilitiesDevelop and execute verification plans for analog and mixed-signal IPs and SoCsCreate, maintain, and enhance AMS verification environments using industry-standard methodologiesDevelop behavioral models of analog blocks using Verilog-A, Verilog-AMS, SystemVerilog RNM, or equivalent modeling languagesDesign testbenches, stimuli, checkers, assertions, and coverage metrics to validate mixed-signal functionalityPerform functional, corner, Monte Carlo, and regression simulationsCollaborate with analog and digital design teams to identify, debug, and resolve functional issuesSupport integration and verification of analog IPs within larger digital or mixed-signal SoCsAnalyze simulation results and communicate findings through clear technical reportsContribute to verification methodology improvements, automation,



and scriptingSupport silicon bring-up and correlation between simulation and laboratory measurements when requiredRequired QualificationsMaster's degree in Electrical Engineering, Electronics Engineering, or a related fieldSolid understanding of analog and mixed-signal circuit fundamentals, including:Operational amplifiersComparatorsADCs and DACsPLLs (preferred)Voltage regulators and referencesSwitched-capacitor circuitsExperience with AMS simulation and verification tools (e.G., Cadence Virtuoso, Spectre, Xcelium)Knowledge of Verilog-AMS, Verilog-A, SystemVerilog, or Real Number Modeling (RNM)Familiarity with scripting languages such as Python, Tcl, Perl, or ShellStrong debugging and problem-solving skillsGood communication skills and ability to work effectively in cross-functional teamsFluent in EnglishDesirable QualificationsExperience with UVM-based verification environments.Knowledge of digital verification methodologies.Familiarity with mixed-signal modeling techniques and abstraction levels.Experience with low-power verification concepts.Understanding of CMOS device operation and semiconductor fundamentals. xysqume All INVENTVM positions offer a stake in the company equity that also entitles to receive dividends, competitive benefits, sustainable work logistics aimed at balancing personal life and project deadlines.#J-18808-Ljbffr

Vedi l’offerta su Go Lavoro: golavoro.it/annuncio-lavoro/80gs8r