22 set - Vigevano
Ams Italy
ams Italy S.r.l. is seeking a technical leader responsible for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC products.
Invii la sua candidatura dopo aver letto i requisiti di competenza e qualifica per questa posizione, riportati di seguito.
You will define architectures, lead RTL design and integration, and drive design reviews to ensure quality. The ideal candidate has MSc or PhD in Electrical Engineering with 10+ years of digital IC design experience, xysqume strong Verilog/SystemVerilog skills, and hands-on experience with high-speed interfaces and timing
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