22 set - Bardi
Altro
ams Italy S.r.l. seeks a Technical Leader for architecture and RTL development of high-speed digital subsystems in communication ICs and mixed-signal SoCs. You will define digital architectures, lead RTL integration, and drive design reviews while supporting verification teams.
The role requires a PhD/MSc in EE with 10+ years in digital IC design, RTL in Verilog/SystemVerilog, and experience with FinFET/FD-SOI nodes. Knowledge of UCIe/PCIe interfaces is advantageous.
25 set - Pescara
NOVAMEDICA
25 set - Fermo
Adecco Italia
25 set - Trentino-Alto Adige
Chino.Io
25 set - Padova
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