22 set - Bardi
Altro
ams Italy S.r.l. is seeking a Technical Leader to own architecture and RTL development for high-speed digital subsystems in communication ICs and mixed-signal SoCs. You will define architectures and lead RTL design, ensuring integration and adherence to quality standards.
The role requires 10+ years of digital IC design experience, strong Verilog/SystemVerilog skills, and expertise in high-speed interfaces and timing analysis. FinFET/FD-SOI experience is preferred.
25 set - Roma
DAVID NAMAN
25 set - Udine
OLTRE I CONFINI 2.0
25 set - Friuli-Venezia Giulia
Arethusa
25 set - Pescara
Alll