24 set - Canneto Pavese
Ams Italy
ams OSRAM is seeking a technical leader to architect and drive RTL development for high-speed digital subsystems in communication ICs and mixed-signal SoCs. You will define digital architectures, lead RTL efforts, and mentor engineers on design reviews and quality standards.
The role requires MSc/PhD in Electrical Engineering with 10+ years in digital IC design, Verilog/SystemVerilog proficiency, and experience with high-speed interfaces.
#J-18808-Ljbffr
25 set - Roma
DAVID NAMAN
25 set - Udine
OLTRE I CONFINI 2.0
25 set - Friuli-Venezia Giulia
Arethusa
25 set - Pescara
Alll