26 set - Cascina Priora
Infineon Technologies
Infineon Technologies in Italy is seeking a Principal Digital Design Engineer to lead the RTL/Verilog design of advanced Analogue/Mixed‑Signal IPs and drive silicon bring‑up.
You will own the full digital design flow RTL‑to‑GDS, coordinate with System and Analogue teams, and mentor engineering staff to achieve robust timing closure and design excellence.
The role requires 10+ years of RTL experience and fluent English, with a strong leadership mindset and hands‑on expertise in high‑speed SerDes.
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