Senior Digital IC Design Engineer (RTL/Verilog)

27 set - Catania
Nxp Semiconductors

NXP Semiconductors in Italy (Catania) is seeking a Master’s-level IC design engineer to develop digital sub-circuits for SOCs using Verilog/SystemVerilog, RTL techniques and advanced verification.

You will collaborate with analog, mixed-signal and software teams to optimize interfaces, perform design verification, participate in post-silicon validation and contribute to high-quality, testable ICs.

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