26 set - Italia
Nokia
Nokia in Bari, Puglia is seeking a SoC Physical Design Engineer to drive floorplanning, placement, routing, and timing closure for cutting-edge Optical Network ASICs.
You will translate RTL to GDSII, optimize power, performance and area, and collaborate with logic/design teams on feasibility and trade-offs.
The role demands 3+ years in ASIC physical design on 3/5/7nm nodes, strong scripting (Python/TCL) and experience with Fusion Compiler or Innovus, Primetime, Calibre, and Redhawk.
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