SoC Physical Design Engineer – Floorplanning, P&R & Timing

29 set - Magliano in Toscana
Nokia

Nokia is seeking a SoC Physical Design Engineer in Livorno, Toscana, Italy to implement physical design for Optical Network ASICs.
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You will handle floorplanning, placement, routing, and timing closure while collaborating with RTL and hardware teams and driving PD methodologies across 3/5/7nm nodes. xysqume

The role emphasizes automation, verification rigor, and learning the latest nodes and tools, with flexible hybrid working arrangements and career development opportunities.

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