27 set - Venezia
Infineon Technologies
ppIn this role you will lead end-to-end ADC design and analog/mixed-signal blocks, collaborating with cross-functional teams to bring high-performance converters to silicon.
You'll drive pre- and post-silicon verification, modeling, and architecture decisions that shape product performance and reliability.
The position offers the opportunity to mentor engineers, contribute to cutting-edge ADC tech, and influence design methodology across projects.
This role aligns with Infineon's mission to enable green, secure, and efficient energy through advanced semiconductor solutions.
/pullisalary aligned with collective agreement /lililocation-based compensation /liliperformance-based rewards /liliLead end-to-end ADC design including architecture, circuit implementation, and silicon bring-up for SAR, Pipeline, Sigma-Delta, Flash, or hybrid topologies /liliDesign analog/mixed-signal building blocks (OTAs, comparators, DACs, sample-and-hold, references, clocking/bias) with ownership of performance, power, area, and cost /liliPerform pre-silicon verification from transistor to chip level, including Monte Carlo and corner analyses, and post-silicon lab characterization and debugging /liliDevelop behavioral/architectural models of ADC/mixed-signal blocks using Python and MATLAB for system-level exploration /liliCollaborate cross-functionally with digital design, physical design,
and CAD teams to ensure successful tape-out and align with customer requirements /liliMentor junior and mid-level engineers, lead design reviews, and contribute innovative ideas based on state-of-the-art trends in mixed-signal and ADC design /lili5+ years of hands-on analog and mixed-signal IC design with proven silicon tape-outs and product bring-up /liliStrong expertise in ADC architectures (SAR, Pipeline, Sigma-Delta, Flash, or hybrid) and analog blocks (OTAs, comparators, references, LDOs, switched-capacitor circuits) /liliSolid understanding of mixed-signal design including clock distribution, digital calibration, timing closure, and asynchronous logic /liliProficiency with EDA tools (Cadence Virtuoso/Spectre, ADE XL, HSPICE or equivalent), full custom IC design flow, and experience with advanced CMOS nodes (130nm–12nm) /liliPython and/or MATLAB/Simulink for automation, scripting, and system-level modeling; knowledge of digital calibration techniques /liliCross-functional collaboration /liliMentoring and leadership /liliInnovation and state-of-the-art thinking /liliADC architectures (SAR, Pipeline, Sigma-Delta, Flash, or hybrid) /liliAnalog building blocks (OTAs, comparators, references, LDOs, switched-capacitor circuits) /liliClock distribution and timing closure /li /ulpSenior Staff Engineer Analog Mixed-Signal Design (f/m/div) venezia, veneto, it /p /p #J-*****-Ljbffr
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