30 set - Pavia
Amd
Overview As a Staff Layout Design Engineer in AMD's SerDes Technology Group, you will support high-speed, multi-protocol wireline transceivers for future CPU and GPU connectivity. You'll work within a world-class team to translate circuit requirements into physical layouts and verify performance after placement. You will drive layout methodologies, contribute to productivity improvements, and collaborate with distributed teams across time zones.
This role offers a chance to shape next-gen SerDes solutions at scale, impacting AMD's advanced silicon platforms.
Retribuzione / Benefits ~ AMD benefits at a glance Layout design of high speed and high performance SerDes analog mixed signal circuit per project requirements Block level physical implementation including floor-planning, power distribution, and clock/signal routing Post-layout circuit performance analysis participation Estimate schedules, track progress,
and report status Supervise layout resources and address layout quality issues in collaboration with design teams Strong understanding of analog and mixed signal layout fundamentals (IR, EM, capacitances, RC delay, self-heating) Experience with high-speed signal routing and shielding Proficiency in physical design verifications (LVS/DRC/ERC/ANT/ESD) Familiarity with circuit design concepts/flows and IC manufacturing processes Experience with high-speed SerDes blocks and PLLs in FinFET processes is a plus Experience with digital on top integration or digital SOC flows is a vantaggi Experience with Cadence SKILL and programming (Perl, Python, Tcl) is a plus Ability to collaborate with remote teams across time zones Bachelor in Electrical Engineering (or equivalent) RC delay and self-heating analysis
30 set - Licata
Ernesto
30 set - Casale Monferrato
Ernesto
30 set - Milano
Ernesto
30 set - Lariano
Letuelezioni