Sr. Package Layout Engineer, Annapurna Labs
Pubblicato il 01-10-2026 - Internet / Comunicazione online / E-commerce in Italia
Sr. Package Layout Engineer, Annapurna Labs - AI Silicon Packaging
Annapurna Labs (our organization within AWS) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.
We are seeking a Sr. Package Layout Engineer to lead the end-to-end physical design of advanced IC packages for next-generation machine learning and data center ASICs.
In this role, you will own the package layout from initial floor planning through tape out and manufacturing release. You'll drive the physical implementation of complex multi-die and advanced packaging architectures, working closely with silicon, SI/PI, thermal, and manufacturing teams to deliver production‐ready designs that meet dynamic performance, density, and reliability targets.
Key Job Responsibilities
Lead the full package layout cycle from die floor planning, bump/pad assignment, and RDL routing through substrate design, verification, and tape out release.
Drive physical design of advanced packaging architectures including 2.5D interposer, 3D-IC, fan‐out wafer‐level packaging, and silicon bridge technologies (e.g., CoWoS, EMIB, or similar).
Define and optimize package floorplans considering die placement, bump maps, power/ground distribution, high‐speed signal escape routing, and decoupling capacitor placement.
Perform detailed RDL and substrate routing for high‐density interconnects including microbumps, C4 bumps, TSVs, microvias, and PTH vias across multi‐layer organic substrates and silicon interposers.
Participate in die‐level RDL routing and bump planning in coordination with ASIC physical design teams, ensuring the die‐package interface is co‐optimized for power delivery and signal routing from the earliest des