01 ott - Italia
Altro
In this role, you will implement physical design for Optical Network ASICs across cutting-edge nodes, focusing on power, performance, and area. You will work within a hardware/RTL team to translate designs into silicon and optimize flows for submicron processes. You'll tackle floorplanning, placement, routing, and timing closure, shaping multi-project IP and design methodologies. The opportunity centers on delivering best-in-class silicon while learning the latest nodes and tools. You will contribute to a mission-driven environment that values automation and rigorous verification.
Flexible and hybrid working schemes
Parental leave (90 days) with return option
Life insurance for employees
Well-being programs for mental and physical health
Participation in Nokia Employee Resource Groups (NERGs)
Career development and coaching/mentoring
Perform floorplanning, place & route, and power/clock distribution for blocks and full chips
Execute physical verification, IR/EM analysis, and timing closure at block and chip level
Collaborate with logic designers and hardware teams on feasibility studies and design trade-offs
Evaluate IP vendors, process nodes, and provide actionable recommendations
Develop PD methodologies and automation scripts for steps from Synthesis to GDSII
Conduct static timing analysis, create timing constraints, validate critical paths, and sign off timing
3+ years of experience in ASIC physical design flow and methodologies on 3/5/7nm nodes
Solid knowledge of RTL to GDSII and underlying IC design concepts
Experience with EDA tools: Fusion Compiler or Innovus, Primetime or equivalent, Calibre, Redhawk
Scripting experience in TCL, Python or Perl
Bachelor's degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics
Strong collaboration with cross-functional teams
team collaboration
analytical mindset
problem solving
Floorplanning and placement/routing
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