Intern - AIPU Board Development
Pubblicato il 02-10-2026 - Axelera AI in Firenze
About Us
Axelera AI is not your regular deep-tech company. We are creating the next-generation AI platform to support anyone who wants to help advancing humanity and improve the world around us.
In just five years, we have raised a total of $450 million and have built a world-class team of 250+ employees (including 60+ PhDs with more than 40,000 citations), both remotely from 20 different countries and with offices in Belgium, France, Switzerland, Italy, the UK, headquartered at the High Tech Campus in Eindhoven, Netherlands.
We have also launched our Metis™ AI Platform, which achieves a 3-5x increase in efficiency and performance, and have visibility into a strong business pipeline exceeding $100 million.
Our unwavering commitment to innovation has firmly established us as a global industry pioneer.
Are you up for the challenge?
Position Overview
We are looking for a motivated 6-months Intern Lab Technician to join our hardware team supporting the development of AIPU (AI Processing Unit) boards. You will work closely with hardware and test engineers,
contributing to electrical characterization, test bench setup, and ancillary card design activities, while also helping keep the lab organized and running smoothly.
This is a great opportunity for a technical diploma holder (ITS/Perito) looking to gain hands-on experience in a real R&D; lab environment, working on cutting-edge AI hardware.
Key Responsibilities
- Electrical measurements: Perform voltage, current, power, signal integrity, and timing measurements on AIPU boards and related hardware using lab instrumentation (oscilloscopes, multimeters, power supplies, DAQ systems, etc.)
- Test bench definition and setup: Support the design, assembly, and configuration of test benches for board bring-up and validation activities
- Board performance characterization: Assist in collecting, organizing, and analyzing performance data to validate board behavior against specifications
- Ancillary card schematic entry and