FPGA and Emulation Prototyping Engineer
Pubblicato il 02-10-2026 - NXP Semiconductors in Catania
NXP's Industrial & IoT Edge solutions range from the smallest MCUs to very high-performance processors to provide real-time insights and efficient automation when performance matters most. NXP's advanced portfolio of edge processing solutions lets developers explore their most innovative ideas with confidence, enabling applications across the autonomous home, industrial automation, and personal electronics.
Aumenti le sue possibilità di arrivare alla fase del colloquio leggendo la descrizione completa del lavoro e candidandosi tempestivamente.
NXP is building new teams in Catania to create high impact micro-controllers (MCU) as part of NXP's intelligent AI at the Edge. This team will include a wide range of engineering talent from analog to SOC digital design. Full product development local will product world class products at a world class pace.
We are seeking a skilled and motivated FPGA Prototyping/Emulation Engineer to join our hardware design team. The ideal candidate will have hands-on experience in FPGA-based prototyping and emulation of complex SoC designs,
and will work closely with RTL designers, verification engineers, and software teams to enable early software development and system validation.
The candidate should be able to define, lead, and execute a long-term strategy for pre-silicon validation leveraging emulation and FPGA prototyping platforms. This role will drive the optimization and automation of the emulation infrastructure and enable hardware, software, firmware, and validation teams to efficiently execute and validate complex microcontroller SoCs.
Your Responsibilities.
- Develop, bring-up and maintain pre-silicon Emulation/FPGA-based prototyping platforms like HAPS-100/Veloce/ Palladium/ZeBU or FPGA for IP/SoC.
- Integrate and debug RTL blocks on FPGA platforms (e.g., Xilinx, Intel/Altera).
- Collaborate with design and verification teams to bring up emulation environments.
- Optimize FPGA resource usage and timing closure for large-scale d