Principal Analog IP Design Lead

03 ott - Italia
Nxp Semiconductors

NXP’s Industrial & IoT Edge solutions range from the smallest MCUs to very high-performance processors to provide real-time insights and efficient automation when performance matters most. NXP’s advanced portfolio of edge processing solutions lets developers explore their most innovative ideas with confidence, enabling applications across the autonomous home, industrial automation, and personal electronics.
NXP is building new teams in Catania to create high impact microcontrollers (MCU) as part of NXP’s intelligent AI at the Edge. This team will include a wide range of engineering talent from analog to SOC digital design.
Full product development local will product world class products at a world class pace.
This team will include all key engineering disciplines in Design, Architecture, Verification, DfT and Physical Design to produce high performance and quality products.
We are now hiring for Analog Design IP Leaders : Role Summary:
- Define analog/mixed signal IP requirements based on product requirements.




- Drive and define innovative circuit architectures to meet requirements.
- Create and ensure robust and high-quality IP from requirements.
- May include leading small teams of analog and digital designers to implement solutions.
- End-to-end ownership for the implementation, simulation, layout, and validation of mixed signal IP for microcontrollers (MCUs).
- This IP could be data converters (ADC, DAC), clock generators (crystal oscillators, free running oscillators, PLL) or any other miscellaneous analog or mixed signal IP that adds value to NXP MCUs products.
- Lead engineering lead on IP development including working with other analog, digital and verification resources but also working with the SOC product leads or optimal integration of the IP.
- Implementation of IP including leading design reviews, creating documentation of IPs and support of productization of IPs (production test, life test, etc).

Your Responsibility
- Define specification for IP base

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