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Senior Signalling System Engineer

Pubblicato il 03-10-2026 - Hitachi in Torino

Location

Turin, Piedmont, Italy

Job ID

R0136103

Date Posted

2026-09-21

Company Name

HITACHI RAIL STS S.P.A.

Profession (Job Category)

Engineering & Science

Job Schedule

Tempo pieno

Remote

No

About Us

A career at Hitachi Rail will help create a legacy. With operations in every corner of the world, our work goes to the cutting-edge of digital transformation and technology. From the multi-cultural strength of our global organisation to the sustainable and innovative ways we work to bring people together, there's something for everyone to get stuck into. And that's where you come in.

Job Description

Hitachi Rail is looking for an enthusiastic, self-motivated Senior Signalling System Engineer. The successful candidate will have solid experience in the rail industry, managing wayside installation design and routing cables along the track and within technical rooms. This position is based in Turin, Italy.

Accountabilities
- Technical Leadership: Lead end-to-end ERTMS delivery, acting as the final technical sign-off for subsystem specifications, design,



and integration.
- Project Management: Define, plan, and manage signaling project milestones, budgets, and resources (QCD - Quality, Cost, Delivery).
- System Integration & V&V;: Oversee Verification & Validation (V&V;) activities, including testing and commissioning of ERTMS Level 2/3, GSM-R, and Automatic Train Protection (ATP), CBTC.
- Stakeholder Management: Collaborate with contractors, national railway authorities, and internal teams to ensure compliance with CENELEC standards and regulatory requirements.
- Design & Engineering: Develop or adapt technical solutions, including requirement analysis, RAMS (Reliability, Availability, Maintainability, Safety) management, and application rules
- Requirements Management – Ensure the definition and management of System and Signalling System Requirements; ensure the implementation of Requirements Management Process assuring Signalling subsystems requirements alloc

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