Senior Electronics Design Engineer

03 ott - Grugliasco
Thales

Main mission
To provide deep expertise in FPGA and digital design, strengthening the technical capability of the Electronics domain and evolving the design approach for the digital part of our document readers and biometric scanners. To deliver robust and scalable FPGA architectures that meet product performance, reliability, and schedule requirements
Specific responsibilities
- Define FPGA architecture and detailed design specifications from system requirements
- Design, implement, and maintain RTL in VHDL / Verilog / SystemVerilog
- Develop and execute the verification strategy - verification plan, testbenches, and simulation environments; formal verification where applicable
- Perform synthesis, place‑and‑route, timing analysis, and timing closure
- Integrate and validate product interfaces: sensor interfaces (MIPI CSI-2, SLVS-EC), PCIe, DDR3/4/5, Ethernet, UART/SPI/I2C
- Implement image/streaming data processing along the sensor data path on FPGA
- Optimize FPGA resource utilization, power consumption, and performance
- Support board bring‑up, debugging,



and system integration together with electronics and board‑design engineers
- Develop automation scripts (Python, Tcl, Bash)
- Document design decisions, verification results, and engineering processes
- Participate in technical planning, risk assessment, and project execution activities
- Evaluate and introduce current FPGA practices, tools, and technologies to improve development efficiency and product quality
- Promote engineering practices and technical standards within the domain

Education
Bachelor's or Master's degree in Electronics, Electrical/Computer Engineering, or a related discipline
Experience Level
Proven experience (8+ years) of FPGA design and development, spanning the full cycle: architecture through timing closure and hardware validation
Competences
Technical / functional skills:
- Strong command of RTL (VHDL / Verilog / SystemVerilog) and verification methodology
- Solid grounding in core dig

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