Design Engineer
Pubblicato il 03-10-2026 - 1460 Micron Semiconductor Ital in Avezzano
Department Introduction
The Non-Volatile NAND Design Engineering group is responsible for the design and optimization of analog, digital and mixed-signal circuits enabling advanced NAND Flash memory products. Close collaboration with cross-functional teams ensures scalable, manufacturable, and reliable solutions across technology nodes.
Position Overview
As a Design Engineer in the NVE Design Engineering Datapath group at Micron Semiconductor Italia, you will contribute to the development of best‑in‑class NAND Flash memory products, focusing on datapath architectures and high‑speed interfaces. In this role, you will support the design, optimization, and validation of NAND datapath logic and DDR high‑speed interfaces, working at block and sub‑system level and contributing to full‑chip integration. You will apply your expertise in high‑speed CMOS circuits, timing, signal integrity, and power optimization, using both industry‑standard tools and Micron‑proprietary methodologies.
Responsibilities
Responsibilities include, but not limited to:
- Design and optimize high-speed datapath and interface circuits, ensuring timing closure and performance at block and sub‑system level.
- Translate system and interface requirements into circuit architectures and transistor‑level implementations, balancing performance, power, and area.
- Perform functional, timing, and signal integrity verification using advanced simulation methodologies (including PVT and corner analysis).
- Collaborate with multi‑functional teams to ensure accurate floorplan integration, manufacturability, and alignment with product specifications.
- Develop and apply automation solutions (e.g., scripting, AI‑assisted methodologies) and support silicon validation, debug, and documentation.
Min Qualifications
- M.S. or Ph.D. in Electrical Engineering, Electronics, or a related field.
- Strong knowledge of high‑speed digital, analog, and mixed‑signal CMOS circuit design.
- Solid understanding of timing, signal inte