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Staff Layout Engineer

Pubblicato il 04-10-2026 - Advanced Micro Devices in Milano

ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.
Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.
STAFF LAYOUT DESIGN ENGINEER
THE ROLE:
The AMD SerDesTechnology Group develops high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS process. We are currently seeking an experience analog/mixed-signal layout design engineer to join ourworld-class team in the development of SerDes solutions to facilitate the future connectivity of AMD CPU and GPU products.
THE PERSON:
You have a passion for high speed layout design with innovative and creative ideas to solve complex design challenges.



You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills, and are willing to learn, and ready to take on problems.
KEY RESPONSIBILITIES:
- Layout design of high speed and high performance SerDes analog mixed signal circuit in accordance to project requirements and specifications.
- Block level physical implementation which includes floor-planning, power distribution network, clock and signal routing, analog and mixed signal transistor level layout.
- Participate in post-layout circuit performance analysis.
- Participate in block/IP/chip level integration activities.
- Estimate realistic schedule, track and report clear progress and status.
- Strong participation in defining layout methodology and flow.
- Driving layout productivity improvement initiatives (i.e., pcell development and automa

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