ENGINEER, DESIGN Avezzano, L'Aquila, Italy Posted 19 hours ago
Pubblicato il 04-10-2026 - Elettrotecnica in Avezzano
ENGINEER, DESIGNAvezzano, L'Aquila, ItalyApply NowFind out how well you match with this jobJob ID: JR103685Our vision is to transform how the world uses information to enrich life for *all*.Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Design/Senior Design Engineer – NAND digital (NVE Engineering)Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.Department IntroductionThe Non-Volatile NAND Design Engineering group is responsible for the design and optimization of analog, digital and mixed-signal circuits enabling advanced NAND Flash memory products.
Close collaboration with multi-functional teams ensures scalable, manufacturable,
and reliable solutions across technology nodes.Position OverviewAs a Logic Design Engineer in the NVEG organization at Micron Semiconductor Italia, you will play a key role in the definition, implementation, verification, and silicon validation of NAND Flash logic features.
In this role, you will act as a technical owner of complex logic functionalities, working at the intersection of architecture, firmware, datapath, analog, and test teams. You will contribute to new product pathfinding, ensure robust feature implementation across technology generations, and support silicon bring‐up, validation, and learning.ResponsibilitiesResponsibilities include, but are not limited to:
- Own end-to-end development of logic features, from architecture definition through RTL implementation, verification, and post-silicon validation.
- Translate system and firmware requirements into micro-architecture specifications and robust digital imp