06 ott - Località Vignazza
Fondazione Chips-IT
pFONDAZIONE CHIPS-IT seeks a CAD EDA Flow Engineer to manage and optimize the EDA infrastructure for advanced SoC design up to tape-out. /ppYou will liaise with Cadence, Synopsys and Siemens, install and maintain PDKs across digital, analog and RF workflows, and support foundries for DRC/LVS and tape-out readiness. The role is based in Italy, with options between Pavia and Bologna. /ppYou will also create internal trainings and documentation to accelerate design teams and evolve design flows. /p #J-18808-Ljbffr
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