Senior SerDes
Pubblicato il 06-10-2026 - Altro in Trento
About the Role
Per essere preso/a in considerazione per un colloquio, la preghiamo di assicurarsi che la sua candidatura sia pienamente in linea con le specifiche del lavoro riportate di seguito.
We are looking for a highly motivated
Senior SerDes & High-Speed PHY Validation Engineer
to play a key role in validating next-generation high-speed connectivity solutions for cloud, AI, and data center networking systems.
In this role, you will lead the validation and characterization of advanced Ethernet SerDes technologies spanning 112G PAM4 and next-generation 224G PHY architectures. You will work at the intersection of silicon design, signal integrity, system engineering, and validation, driving complex technical investigations from first silicon bring-up through compliance and product readiness.
This opportunity is ideal for engineers who enjoy combining deep signal integrity knowledge, hands-on lab ownership, automation development, and cross-functional technical leadership to solve challenging high-speed design and validation problems.
What You'll Do
Lead SerDes Validation and Characterization
Drive end-to-end validation of high-speed Ethernet SerDes and PHY solutions across silicon, package, board, and system environments.
Define and execute validation strategies for 112G PAM4 and next-generation 224G technologies.
Develop characterization methodologies to assess performance, robustness, and design margins across operating conditions.
Support silicon bring-up activities and root-cause analysis of complex system-level issues.
Execute Advanced High-Speed Measurements
Perform and analyze:
Eye-diagram measurements
BER and margin analysis
Bathtub curve characterization
Jitter decomposition (RJ, DJ, TJ)
CTLE and DFE performance evaluation
TX FIR optimization
Channel loss and equalization analysis
Debug Complex Signal Integrity Challenges
Investigate and resolve performance limitations across:
Silicon
Package
PCB channels
Connectors
Cables
End-to-end system inte