06 ott - San Michele All'adige
Xsight Labs
About the Role
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We are looking for a motivated SerDes & High-Speed PHY Validation Engineer to join our high-speed connectivity validation team and contribute to the development of next‑generation Ethernet networking solutions for cloud, AI, and data center applications.
In this role, you will participate in the validation and characterization of advanced Ethernet SerDes technologies spanning 112G PAM4 and next generation 224G PHY architectures. You will work closely with validation, design, signal integrity, and system teams to ensure robust and compliant high‑speed communication solutions from first silicon bring‑up through product readiness.
This opportunity is ideal for engineers who enjoy hands‑on lab work, high‑speed measurements, signal integrity challenges, and collaboration across multiple engineering disciplines.
What You'll Do
Perform SerDes Validation and Characterization
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- Execute validation activities for high‑speed Ethernet SerDes and PHY solutions across silicon, package, board, and system environments.
- Perform characterization testing to evaluate performance, robustness, and design margins across operating conditions.
- Support silicon bring‑up and debug activities.
- Contribute to root‑cause investigations and issue resolution.
Execute Advanced High‑Speed Measurements
Perform and analyze:
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- Eye‑diagram measurements
- BER and margin analysis
- Bathtub curve characterization
- Jitter decomposition (RJ, DJ, TJ)
- CTLE and DFE performance evaluation
- TX FIR optimization
- Channel loss and equalization analysis
Debug Signal Integrity Challenges
Assist in investigating performance limitations across:
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- Silicon
- Package
- PCB channels
- Connectors
- Cables
- End‑to‑end system interconnects
Work closely with design and architecture teams to support technical investigations and des
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