07 ott - Padova
Infineon
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Join the thinkers, builders, and problem solvers behind tomorrow’s technology.
As a SoC Physical Implementation Engineer in our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life.
Are you in?
Your roleKey responsibilities in your new role
You will join a dynamic and growing team where you will own the Digital Physical Design work packages.
• Perform Floor planning, Partitioning, Placement & Routing at chip & block level
• Optimization of Timing, Power, Area according to the design specifications
• Achievement of Timing Closure and execution of Verification and Sign-off
• Development of P&R; scripts for development flow automation
• Close Cooperation with digital design and synthesis team and analog layout team for smooth execution in a mixed Digital and Analog development flow
• Participation in Design Reviews, FMEA, and generation of Design Reports
• Effort estimation, planning of related work package, interfacing of project team
Your profileQualifications and skills to help you succeed
You are a highly motivated and results-driven team player with strong analytical and problem-solving skills. You thrive in international and cross-functional environments, using your creative and open-minded approach to drive innovation, collaboration, and successful outcomes.
• A degree in Electrical/Electronic Engineering or equivalent field of study with specific knowledge of microelectronic devices and related digital circuit design
• At least 3 years of experience in implementing SoC designs from RTL to GDS, preferred in a UNIX environment
• Solid Experience of the RTL to GDS flow: synthesis, P&R;, STA and sign-off checks in sub-micron technologies using either the Synopsys or Cadence tool chain
• Previous experience with physical design work-packages planning, including ef
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