Sr Staff Digital Design Engineer
Pubblicato il 07-10-2026 - Renesas Electronics in Catania
Job Description
We are looking for a talented Snr Staff Digital Design Engineer with a BSc/MSc in Electrical/Computer Engineering (EE/ECE) and industry experience of 8-12 years. Successful candidate will be reporting to the Snr Manager of Design Engineering.
Our team works on the most advanced digital power management ICs in the industry. This is an excellent full-time/permanent role giving the opportunity to work with an expert team pushing the envelope of digital design, verification, debug, simulation, and automation script development and thus contributing to industry leading chips.
Job Duties
- Develop, debug, and verify digital designs in pre and post silicon environment
- Write tests to verify bulk design intent as per specification.
- Learn, develop and improve scripts to facilitate design automation flows.
- Manage assigned design blocks in design requirements, architecture, and implementation
- Research and present new tools in aid of design development process
- Act as technical mentor for junior engineers.
- Represent digital design as functional digital design lead in design projects.
Qualifications
- BSc/MSc in Electrical Engineering/Computer Engineering (EE/ECE) and 8-12 years of relevant industry experience
- Prior design project work experience showing collaborative and innovative thinking
- Proficient in developing CDC / RDC / LINT clean designs in Verilog
- Comfortable with debugging mixed-signal designs in System Verilog based test benches
- Exposed to gate level simulation debug.
- Experience in designing industry standard serial interfaces (I2C, I3C, SPI, I2S etc)
- Strong analytical skills and debug methodology
- Good written and verbal communications skills
- Working experience with Cadence or Synopsys design tool flows.
- Hands-on technical leadership role resulting in successful projects.
Preferred skills
- Proficient in scripting languages such as Python/Perl
- Knowledge of ARM cortex M-series processor and computer architecture in gener