09 ott - Vigevano
Ams Italy
ams Italy S.r.l.
Sta pensando di candidarsi per questo lavoro? Verifichi tutti i dettagli nella descrizione e poi faccia clic su "Candidati".
is seeking a technical leader responsible for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC products.
You will define architectures, lead RTL design and integration, and drive design reviews to ensure quality.
The ideal candidate has MSc or PhD in Electrical Engineering with 10+ years of digital IC design xysqume experience, strong Verilog/SystemVerilog skills, and hands-on experience with high-speed interfaces and timing
#J-18808-Ljbffr
13 ott - Campo di Ne
Bipiemme Communication
13 ott - Bolzano
Jobtech
13 ott - Moggio Udinese
Intervieweb
13 ott - Montà
Medicina