Senior Digital Design Engineer

Vedi l’offerta su Go Lavoro: golavoro.it/annuncio-lavoro/8bl3k2

Overview

In this role you will help design and implement advanced digital subsystems for automotive and industrial electrification. You will collaborate with architects, verification engineers, and cross-functional teams to define digital architecture and ensure robust RTL in SystemVerilog. You will address performance, power, area, safety, and testability trade-offs and drive design quality through verification and sign-off readiness. This position offers impact across mixed-signal projects, reuse of digital IP, and contribution to safety-compliant automotive developments. You will work in a global, collaborative environment focused on delivering high-quality mixed-signal solutions at scale.Retribuzione / Benefits

equal pay commitmentannual incentive opportunitiesequitycompetitive benefits packagefair remuneration practicesResponsabilità

Develop RTL designs for complex digital blocks and subsystems using SystemVerilog/VerilogContribute to digital architecture definition with senior designers and system architectsAnalyze design trade-offs for performance, power, area, safety, and testabilityImplement clocking, reset, and power management strategiesSupport IP integration and subsystem-level developmentPerform RTL verification activities including simulation, lint, CDC,



and synthesis checksCollaborate with digital verification engineers for coverage and qualitySupport timing closure and implementation activitiesParticipate in design reviews and sign-off readinessSupport silicon bring-up, debugging, characterization, and root-cause analysisWork within mixed-signal project teams and promote reuse of digital IPs and methodologiesContribute to requirements definition and feasibility analysisSupport multiple development phases from concept through production releaseFollow automotive standards for functional safety and qualityProvide technical guidance to less experienced engineersCollaborate across international R&D; sitesRequisiti fondamentali

Master's degree in Electrical Engineering, Electronics Engineering, or equivalentMinimum 7 years of experience in digital IC designStrong experience with RTL development using SystemVerilog/VerilogExperience with synthesis, timing constraints, and digital implementation flowsUnderstanding of CDC, reset strategies, and low-power design conceptsFamiliarity with DFT fundamentals and design-for-test methodologiesExperience in mixed-signal IC development environmentsKnowledge of digital verification methodologies and simulation-based verificationExperience with industry-standard EDA tools (Synopsys, Cadence, Siemens EDA)Fluent written and spoken EnglishTeam collaborationCross-functional communicationMentoring and knowledge sharingSystemVerilog/Verilog RTL developmentSynthesis and timing constraintsDigital implementation flows

Vedi l’offerta su Go Lavoro: golavoro.it/annuncio-lavoro/8bl3k2