09 ott - Catania
Nxp Semiconductors
Role Summary The Senior Layout Engineer is a highly skilled technical contributor responsible for the physical implementation of complex analog, mixed-signal, and custom IC designs. Working with a high degree of independence, this role drives layout execution from floorplanning through tape-out, ensuring that performance, quality, reliability, and schedule objectives are achieved. The position requires strong expertise in advanced layout methodologies, excellent problem-solving capabilities, and effective collaboration with design, verification, and technology teams.
In addition to delivering critical project milestones, the engineer provides technical guidance to less experienced engineers, contributes to methodology improvements, and plays a key role in mitigating project risks and supporting successful silicon delivery. Lead the layout implementation of complex analog, mixed-signal, and custom digital blocks. Drive floorplanning, device matching, routing strategies, and layout optimization to meet performance, area, power, reliability, and manufacturability requirements.
Perform and review physical verification activities, including DRC, LVS, ERC, EM/IR, latch-up, density, and reliability checks. Collaborate closely with design, verification, technology, and product engineering teams to resolve layout-related challenges and achieve project milestones. Provide technical guidance and mentorship to junior engineers and contractors.
Assess project risks, estimate layout effort, and drive execution to meet aggressive schedules. Strong expertise in analog layout techniques, matching, shielding, noise isolation, ESD-aware layout, power distribution, and high-performance routing. Proficiency with industry-standard EDA tools and physical verification flows.
Ability to independently make technical trade-offs and solve complex implementation issues. Influences project execution and physical design methodologies across multiple programs. Plays a key role in achieving project schedules and silicon quality targets.
Approximately 8-12+ years of custom analog/mixed-signal layout experience in deep sub-micron CMOS. Strong knowledge of matching, common centroid, shielding, EM/IR, high-speed routing, parasitics, and DFM practices. Proven experience leading analog-on-top and digital-on-top chip layouts.
Experience with floorplanning, power distribution, ESD, and multiple voltage domains. Fluent in English. SKILL or Perl scripting is a plus. NXP is committed to equal pay for equal work and work of equal value and applies fair, consistent and transparent remuneration practices.
As of the date of this posting, the estimated gross annual base salary range for this position in Italy is between 50,600 € and 69,600 € annually. Actual compensation may vary based on qualifications, experience, skills, and specific business or organizational needs. Where relevant, the total compensation package may also include additional elements such as annual incentive opportunities and/or equity, along with a competitive benefits package.
NXPI) enables a smarter, safer, and more sustainable world through innovation. As the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets. We believe that a key component to growing our business is to develop our people.
To enable you to grow your career at NXP, we offer online and offline learning opportunities to help you develop some of your core and professional skills. We recognize NXP is a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future.
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